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 | "Description" by Radar (1992 pt) | 2020-Jul-21 18:18 |
Sun Ultra SPARC III
64-bit open standards-based SPARC® V9 with VIS™ Instruction Set
4-way superscalar
14-stage non-stalling pipeline
Advanced RAS features
MP scalability: architecturally designed for >1000 CPUs/system
System bus: Sun™ Fireplane Interconnect
Processor memory bandwidth scales with number of processors
Integrated memory controller
L1 caches: integrated instruction (32 KB) & data (64 KB)
L2 cache: 8 MB external (2 way, set-associative)
Clock frequencies: 900 MHz, 1050 MHz and 1.2 GHz
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